Many memory manufacturers are developing multiple-bit-per-cell (MBPC) memories to increase storage density and lower memory cost. MBPC Flash memories, for example, have greater storage density than do binary memories because MBPC Flash memory cells are substantially the same as the binary Flash memory cells but each MBPC memory cell stores multiple data bits. MBPC Flash memories, however, require write and read circuits that can precisely set and sense the threshold voltages of the memory cells.
One goal for MBPC memories is to achieve the required precision for writing and reading data while still providing acceptable performance. Achieving the desired speed and accuracy for writing data in a Flash memory can be particularly difficult since the time required to program a memory cell to a target threshold voltage generally depends on the difference between the target threshold voltage and the threshold voltage of the erased state. Programming to a high threshold voltage from the erased state generally takes more time than does programming to a lower threshold voltage if the same programming parameters are employed for both programming operations. For example, a word line programming voltage Vpp that is high enough to program a memory cell to the highest threshold voltage state within an available time budget, will program a memory cell to a lower threshold voltage state in much less time than the available time budget. The programming accuracy of the lower threshold voltage is generally poor because the programming induces fast changes in the threshold voltage that can overshoot the lower threshold voltage.
One technique that improves programming accuracy for the lower target threshold voltages adjusts the word line voltage Vpp according to the data value being programmed. A higher word line programming voltage Vpp can program a memory cell to the highest target threshold voltage with a time approaching the limits of the available programming time budget. A lower word line programming voltage Vpp can similarly program a memory cell to a lower target threshold voltage in a time about equal to the available programming time budget. Varying the word line voltage according to the multi-bit data value provides good accuracy during programming since the programming rate (i.e., the change in threshold voltage per time) is minimized for each data value.
Varying word line voltage Vpp according to the multi-bit data value is difficult in MBPC memories having continuous word lines because typically multiple memory cells associated with the same word line must be simultaneously programmed to achieve an acceptable data rate. For example, a 2-bit-per-cell memory with a 32-bit data path generally programs 16 memory cells in parallel to provide an acceptable write speed. Programming methods that require word line voltages that vary according to a multi-bit data value are unsuited for parallel programming of two or more memory cells on the same word line because different memory cells are generally programmed in parallel to different multi-bit data values. Accordingly, such MBPC Flash memory architectures must either sacrifice write speed to achieve programming accuracy especially for the lower threshold voltage targets or sacrifice programming accuracy (especially for lower target threshold voltages) to achieve the desired write speed. Such sacrifices make increasing the number of storage bits per memory cell difficult and therefore hamper increases in storage density.
Programming methods and circuits that provide high write speeds and high programming accuracy are sought.